1 Overall system design and working principle
One of the main goals of this system is to realize the miniaturization of the system. For this purpose, hardware compression is used, and the core chip is the sz1510 high-performance compression coding chip of zepax. sz1510 can work in multiple modes such as mjpeg, mpeg-1 encoding and video encoding in vcd format. The mjpeg encoded image quality is very good, but the code rate is very high, requiring large-capacity disk storage, because disk storage has high requirements on the working environment In the airborne environment, if disk storage is used, corresponding shock absorption, constant temperature and other protective equipment must be added, which leads to a large increase in volume, and mpeg-1 encoding has a high compression ratio, a relatively low bit rate, and the image quality meets actual needs. Due to the system design requirements, this system uses the mpeg-1 encoding scheme. At the same time, the use of large-capacity semiconductor memory greatly reduces the size of the system, improves the system's seismic resistance and reliability, and realizes the miniaturization of the system.
The overall structure of the system is shown in Figure 1. The hardware circuit mainly includes five parts: video and audio decoding unit, compression coding unit, decoding logic and interface unit, control unit, and storage unit.
After the system is powered on, som2386 initializes the audio and video encoding module. After the system starts normally, saa7113 decodes the input composite video signal to generate a ccir-601 digital video stream, and ak4550 collects the input analog audio signal to generate a pcm digital audio stream. After being sent to the compression encoding chip sz1510 and compressed into a mpeg-1 system stream, it is stored in an electronic hard disk as a file under the control of som2386.
2 Hardware design
In order to improve the maintainability of the system and reduce the maintenance cost, the hardware structure of this system adopts a modular design method, and the system is divided into 3 modules:
a) Video and audio decoding and compression coding modules: including saa7113, mk2703, ak4550, sz1510, sdram;
b) Logic connection, conversion and interface module: including epm7128, max232, rs232 interface, ide interface, control, status signal interface;
c) Control and storage module: including som2386 and electronic hard disk.
Each module is made into a relatively independent circuit board, and the modules are connected by connectors. If a module in the system fails, you only need to replace the module without replacing the entire system, which is conducive to saving time and reducing costs.
2.1 Design of video and audio decoding and compression decoding
The video decoder adopts saa7113 of philips company, which is a programmable video processing chip, which can be programmed and controlled through a simple i2c bus, with 4 video inputs, anti-aliasing filtering, automatic clamping and gain control, multi-standard The functions of decoding and brightness, contrast and saturation control bring great convenience to the system design. It samples the input PAL standard composite video signal and generates 8bit / pixel ccir-601 digital video stream after decoding (color Space is ycbcr, sampling is 4: 2: 2), sent to the digital video input interface of the video compression chip sz1510, its input clock is provided by the active crystal oscillator of 24.576mhz, and it provides field synchronization signal vs and line synchronization signal hs for sz1510 At the same time, the 27mhz pixel clock is divided into two ways: one way is directly output to sz1510, as its internal digital video sampling clock; the other way through the phase-locked loop clock chip mk2703 to 48khz clock amclm, as the audio codec chip ak4550 System clock, in order to achieve accurate synchronization of video and audio, sz1510 uses the i2c bus simulated by its gpio interface to initialize saa7113.
The audio decoder uses ak4550, which performs high-signal-to-noise ratio 16-bit digital sampling on analog audio to generate pcm digital audio streams.
Compression coding is composed of chip sz1510 and video frame buffer sdram (1m & TImes; 16bit). Sz1510 is a high-performance mjpeg and mpeg-1 coding chip that supports multiple working modes and bit rate modes. The internal is mainly composed of video coding core, tms320c54x High-performance dsp core, interface circuit, dma controller and clock generation circuit, etc. The structure of the video coding core is shown in Figure 2.
sz1510 firstly converts the video stream input into it into video frames of cif format through video preprocessing, automatic cropping, scene switching detection, and then, after motion estimation, motion compensation, discrete cosine transform / inverse discrete cosine transform and variable length Encoding and other processing, generate mpeg-1 video elementary stream and store it in sdram, at the same time, dsp core completes mpeg-1 audio encoding and mpeg-1 format audio / video combination, generates mpeg-1 format system stream, and then passes The fifo buffer with an output port size of 256b is used for data output. During normal operation, a frdy (fifo read) interrupt is generated when the fifo is full to notify the host to read the data in the fifo. The host reads the data_out register through z56 times Taken, when sz1510 sends an eod (end of data) interrupt, the data transmission ends.
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