We will investigate how to trade conduction power in a synchronous buck power stage, which is related to the duty cycle and FET resistance ratio. Performing this compromise process yields a very useful starting point for FET selection. Typically, as part of the design process, you have a set of specifications that include the input voltage range and the desired output voltage, and you need to select some FETs. In addition, if you are an IC designer, you will also have a budget that specifies the FET cost or package size. These two inputs will help you choose the total MOSFET chip area. These inputs can then be used to optimize the efficiency of each FET area.
Figure 1 Conduction loss versus FET resistance ratio and duty cycle
First, the FET resistance is inversely proportional to its area. Therefore, if you assign a certain total area to the FET and you make the high side area larger (to reduce its resistance), the area on the low side must
Decrease while its resistance increases. Second, the percentage of the high side and low side FET conduction times is related to the VOUT/VIN conversion ratio, which is first equal to the high side duty cycle (D). The high-side FET turns on D percentage time, while the remaining (1-D) percentage time is turned on by the low-side FET. Figure 1 shows the normalized conduction losses associated with the FET area percentage (X-axis) and the conversion factor (curve) dedicated to the high-side FET. Obviously, under a certain set conversion ratio, the optimal chip area distribution can be achieved between the high side and the low side, at which time the total conduction loss is minimal. Use a low high side FET for low conversion ratios. Conversely, when using high conversion ratios, use more FETs at the top. Area allocation is critical because if the output is increased to 3.6V, the circuit optimized for 12V: 1.2V conversion ratio (10% duty cycle) will have a 30% increase in conduction losses, and if the output is further increased to 6V, Then the conduction loss will increase by nearly 80%. Finally, it should be noted that all curves pass through the same point when 50% of the high side area is allocated. This is because the two FET resistors are equal at this point.
Figure 2 There is an optimal area ratio based on the conversion ratio.
Note: the resistance ratio is inversely proportional to the area ratio
From Figure 1, we know that the best conduction loss extreme occurs when the 50% conversion ratio is used. However, under other conversion ratio conditions, the loss can be reduced below this level. The mathematical calculation method for this optimization is given in Appendix 1, and Figure 2 shows the calculation results. Even at very low conversion ratios, a significant portion of the FET chip area should be used for high side FETs. The same is true for high conversion ratios; there should be a large portion of the area for the low side. These results are preliminary studies of this problem, which do not include various specific resistance values ​​between the high-side and low-side FETs, the effects of switching speeds, or the cost and resistance associated with packaging such chip areas. Many aspects. However, it provides a good starting point for determining the resistance ratio between FETs and should achieve a better overall compromise in FET selection.
Next time, we will discuss how to determine the leakage inductance requirements of the coupled inductor used in SEPIC, so stay tuned.
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