Current circuit densities of millions of gates, transceiver data rates above 6 Gbps, and other considerations affect system designers' mechanical and electrical board-level design efforts. Dies, chip packages, and circuit boards constitute a closely linked system. In this system, to fully implement the functions of the FPGA, the PCB board must be carefully designed.
When designing with high-speed FPGAs, it is important to consider several design issues before and during board development. These include: reducing system noise by filtering and evenly distributing sufficient power across all devices on the PCB; properly terminating signal lines to minimize reflections; and minimizing crosstalk between traces on the board; Reduce the effects of ground bounce and Vcc reduction (also known as Vcc depression); correctly match the impedance on high-speed signal lines.
Anyone designing an IC package for an extremely high performance FPGA must pay particular attention to the trade-off between signal integrity and versatility for all users and applications. For example, Altera's largest Stratix II GX device is available in a 1,508-pin package and operates down to 1.2V with 734 standard I/Os and 71 low-voltage differential signaling (LVDS) channels. It also has 20 high-speed transceivers that support data rates up to 6.375 Gbps. This allows the architecture to support many high-speed network and communication bus standards, including PCI Express and SerialLite II.
In the design, users can reduce crosstalk by optimizing the pin arrangement. The signal pins should be placed as close as possible to the ground pins to shorten the loop length in the package, especially important high-speed I/Os. In high-speed systems, the main source of crosstalk is the inductive coupling between the signal paths within the package. When the output is converted, the signal must find the return path through the power/ground plane. The change in current in the loop creates a magnetic field that causes noise on other I/O pins near the loop. This situation is exacerbated when the output is converted at the same time. Because the smaller the loop, the smaller the inductance, so that the package of the power or ground pins close to each high-speed signal pin can minimize the effects of crosstalk on nearby I/O pins.
To minimize board costs and maximize system signal integrity for all signal paths, careful design and construction of board materials, layer numbers (stacking), and layout are required. Sending hundreds of signals from the FPGA to or around the board is a difficult task and requires the use of EDA tools to optimize pin placement and chip placement. Sometimes a slightly larger FPGA package can reduce board cost because it can reduce the number of board layers and other board processing limitations.
A high-speed signal path on the PCB, represented by an on-board trace, is very sensitive to interruptions, such as vias between the circuit board layer and the board connector. These and other interrupts will reduce the edge rate of the signal and cause reflections. Therefore, designers should avoid vias and via stubs. If vias are unavoidable, the via leads should be as short as possible. When routing differential signals, use one via of the same structure for each path of the differential pair; this causes the signal interruption caused by the via to be in common mode. If possible, blind holes are used at conventional through holes. Or use back drilling, as the loss of via roots will cause fewer disruptions.
In order to improve the signal integrity of the clock signal, the following principles should be followed:
Before the clock signal is sent to the board components, keep it on a single board as much as possible; always use one plane as the minimum reference plane.
Send fast edge signals along the inner layer adjacent to the ground plane to control the impedance and reduce electromagnetic interference.
Terminate the clock signal properly to minimize reflections.
It is best to use point-to-point clock traces.
Some FPGAs, such as the Stratix II GX family, have on-chip series termination resistors that support several I/O standards. These on-chip resistors can be set to 25 Ohm or 50 Ohm single-ended resistors supporting LVTTL, LVCMOS, and SSTL-18 or SSTL-2 single-ended I/O standards; in addition, 100 Ohm LVDS and HyperTransport inputs on-chip differential support Matching resistance. Differential transceiver I/Os have on-chip resistors that can be programmed to 100, 120, or 150 ohms, and auto-calibration minimizes reflections.
Using internal resistors instead of external devices has several advantages for the system. On-chip termination eliminates the effects of the leads and minimizes reflections on the transmission line, which improves signal integrity. On-chip termination also minimizes the need for external components, allowing designers to use less resistance, fewer board traces, and reduce board space. In this way, you can simplify the layout, shorten the design cycle, and reduce system costs. With fewer components on the board, board reliability is also enhanced.
Crosstalk suppression
In circuit board design, in order to minimize crosstalk, the microstrip and stripline layouts can follow several guidelines. For the double strip layout, the wiring is performed on two layers of the inner board, and both sides have a voltage reference plane. At this time, it is better that the wires of all adjacent layers use the orthogonal wiring technology to increase the distance between the two signal layers as much as possible. The dielectric material thickness, and minimizes the distance between each signal layer and its neighboring reference plane while maintaining the required impedance.
Figure 1: Guidelines for minimizing crosstalk
Microstrip or Stripline Routing Guidelines
The trace pitch is at least three times the thickness of the circuit board's wiring interlayer dielectric layer; it is best to simulate its behavior in advance using a simulation tool.
Instead of a single-ended topology, critical high-speed networks use differentials to minimize the effects of common-mode noise. Within the design limits, try to match the positive and negative pins of the differential signal path.
Reduce the coupling effect of single-ended signals, leaving a proper spacing (greater than three times the trace width), or routing on different layers (neighboring layer wirings are orthogonal to each other). In addition, the use of simulation tools is also a good way to meet the spacing requirements.
Minimize the parallel length between signal termination signals.
Simultaneous conversion noise
As clock and I/O data rates increase, the number of output transitions decreases accordingly, and the transient current during signal path discharge charging increases. These currents may cause board level ground bounce phenomena, ie, the ground voltage/Vcc momentarily rises/falls. Large transient currents from non-ideal power supplies can cause transient drops in Vcc (Vcc drops or sinks). Several good board design rules are given below to help reduce the impact of these simultaneous conversion noises.
Figure 2: The figure shows the recommended number of signal, power, and ground planes when available I/O is fully utilized.
Configure unused I/O pins as output pins and drive them at low voltage to reduce ground bounce.
Minimize the number of simultaneous conversion output pins and evenly distribute them across the entire FPGA I/O section.
Without a high edge rate, the low-slew-rate of the FPGA output is used.
Vcc is inserted between the ground planes of the multilayer board to eliminate the effect of high-speed stitches on each layer.
Using all layers for Vcc and grounding minimizes the resistance and inductance of these planes, providing a low-inductance source with lower capacitance and noise, and returning logic signals on signal planes that are adjacent to these planes.
Pre-emphasis, balance
The high-speed transceiver capabilities of the state-of-the-art FPGAs make them highly efficient programmable system-on-a-chip components, while also presenting board designers with unique challenges. A key issue, especially related to layout, is the frequency-dependent transmission loss, which is mainly caused by skin effect and dielectric loss. When the high-frequency signal is transmitted on a conductor surface (such as a PCB trace), a skin effect is generated due to the self-inductance of the wire. This effect reduces the effective conductive area of ​​the wire and weakens the high frequency component of the signal. The dielectric loss is caused by the capacitive effect of the dielectric material between the layers. The skin effect is proportional to the square root of the frequency, and the dielectric loss is proportional to the frequency; therefore, the dielectric loss is the main loss mechanism of high-frequency signal attenuation.
The higher the data rate, the more serious the skin effect and dielectric loss. For a 1 Gbps system, the signal level reduction on the link is acceptable, but it cannot be accepted on a 6 Gbps system. However, current transceivers have transmitter pre-emphasis and receiver equalization to compensate for high-frequency channel distortion. They also enhance signal integrity and relax the limits of trace length. These signal conditioning technologies extend the life of standard FR-4 materials and support higher data rates. Due to signal attenuation in the FR-4 material, the allowable trace length is limited to a few inches when operating at 6.375 Gbps. Pre-emphasis and equalization can extend it to more than 40 inches.
Some high-performance FPGAs incorporate programmable pre-emphasis and equalization functions, such as Stratix II GX devices, so they can use FR-4 materials and relax layout restrictions such as maximum trace length to reduce board cost. The pre-emphasis function effectively boosts the high-frequency components of the signal. The 4-tap pre-emphasis circuit in Stratix II GX reduces the scattering of signal components (from one bit to the other). Pre-emphasis circuits provide up to 500% pre-emphasis. Each tap can be optimized to a maximum of 16 levels based on data rate, trace length, and link characteristics.
The Stratix II GX receiver includes a gain stage and linear equalizer to compensate for signal attenuation. In addition to the input gain stage, the device allows board designers to have a maximum 17 dB equalization level and can use any of the 16 equalizer stages to overcome board losses. Equalization and pre-emphasis functions can be used in a concert environment or to optimize a particular link individually.
Designers can change the pre-emphasis and equalization levels in Stratix II GX FPGAs while the system is running, or when card configuration is performed after it is plugged into the backplane or other chassis. This gives the system designer the flexibility to set pre-emphasis and equalization levels to predetermined values ​​automatically. In addition, depending on which slot in the chassis or backplane the board is inserted, these values ​​can also be determined dynamically.
EMI problems and debugging
Electromagnetic interference caused by printed circuit boards is directly proportional to the change in current or voltage over time, as well as the series inductance of the circuit. Efficient board designs may minimize EMI but not necessarily eliminate it completely. Eliminating "intruder" or "hot" signals, as well as properly referencing the ground plane to send signals, can also help reduce EMI. Finally, the use of surface mount components that are common in today's market is also a way to reduce EMI.
Debugging and testing complex high-speed PCB designs has become increasingly difficult, as some traditional board debug methods, such as test probes and “Bed-of-nails†testers, may not be suitable for these designs. This new high-speed design can leverage JTAG test tools with in-system programming capabilities and the built-in self-test capabilities that FPGAs can have. Designers should use the same guidelines to set the JTAG test clock input (TCK) signal as the system clock. In addition, minimizing the length of the JTAG scan chain trace between the output of one device's test data and the other device's test data input is also important.
Successful design using embedded high-speed FPGAs requires ample high-speed board design practices and a full understanding of FPGA capabilities such as pinouts, board materials and stacking, board layout, and terminal modes. The proper use of pre-emphasis and equalization functions of the built-in transceiver is also important. The combination of the above points enables a reliable design with stable manufacturability. Careful consideration of all these factors, together with proper simulation and analysis, can minimize the possibility of accidents in the board prototype and will help alleviate the pressure on board development projects.
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