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A.TTL

The main type of TTL integrated circuits is the transistor-transistor logic gate, and most of the TTL uses a 5V power supply.

1. Output high level Uoh and output low level Uol

Uoh ≥ 2.4V, Uol ≤ 0.4V

2. Input high level and input low level

Uih≥2.0V, Uil≤0.8V

2. CMOS

The CMOS circuit is a voltage control device with a large input resistance and is very sensitive to interference signals, so unused inputs should not be opened, connected to ground or power. The advantage of CMOS circuits is that they have a wide noise margin and a small static power consumption.

1. Output high level Uoh and output low level Uol

Uoh≈VCC, Uol≈GND

2. Input high level Uoh and input low level Uol

Uih ≥ 0.7VCC, Uil ≤ 0.2VCC (VCC is the power supply voltage, GND is the ground)

As can be seen from the above:

In the same 5V power supply voltage, the COMS circuit can directly drive TTL, because the CMOS output is higher than 2.0V, the output low level is less than 0.8V; and the TTL circuit can not directly drive the CMOS circuit, the TTL output is high. If it is greater than 2.4V, if it falls between 2.4V and 3.5V, the CMOS circuit cannot detect the high level, and the low level is less than 0.4V. Therefore, the pull resistor should be added when the TTL circuit drives the COMS circuit. If there are different voltage sources, you can also judge by the above method.

If a 3.3V COMS circuit is used in the circuit to drive a 5V CMOS circuit, such as a 3.3V microcontroller to drive the 74HC, there are several ways to solve this problem. The simplest is to directly convert the 74HC to 74HCT (74 series input). Output the chip shown below, because 3.3V CMOS can directly drive the 5V TTL circuit; or add the voltage conversion chip; there is the I / O port of the microcontroller is set to open drain, and then add the pull resistor to 5V, In this case, the size of the resistor should be adjusted according to the actual situation to ensure the rising edge time of the signal.

Introduction to the three series

The 74 series can be said to be the most common chip we usually touch. There are many types in the 74 series, and the ones we usually use the most are the following: 74LS, 74HC, 74HCT, these three series are at the level. The differences are as follows:

Input level output level

74LS TTL level TTL level

74HC COMS level COMS level

74HCT TTL level COMS level

TTL and CMOS levels

1, TTL level (what is TTL level):

The output level is >2.4V and the output level is <0.4V. At room temperature, the general output level is 3.5V and the output low level is 0.2V. Minimum input high level and low level: input high level >=2.0V, input low level <=0.8V, noise margin is 0.4V.

2, CMOS level:

1 logic level voltage is close to the power supply voltage, 0 logic level is close to 0V. It also has a wide noise margin.

3. Level conversion circuit:

Because the values ​​of high and low levels of TTL and COMS are different (ttl 5v<==>cmos 3.3v), level conversion is required when connecting to each other: it is to divide the level by two resistors, there is nothing high. .

4, OC door:

That is, the collector open circuit circuit, the OD gate, that is, the open-drain gate circuit, must have an external pull-up resistor and a power supply to use the switch level as a high and low level. Otherwise, it is generally only used as a switch large voltage and a large current load, so it is also called a drive gate circuit.

5, TTL and COMS circuit comparison:

1) The TTL circuit is a current control device, and the CMOS circuit is a voltage control device.

2) The TTL circuit has a fast speed and a short transmission delay time (5-10 ns), but the power consumption is large. The COMS circuit is slow and has a long transmission delay (25-50 ns) but low power consumption. The power consumption of the COMS circuit itself is related to the pulse frequency of the input signal. The higher the frequency, the hotter the chip set, which is normal.

3) The locking effect of the COMS circuit:

Due to the input of too much current in the COMS circuit, the internal current increases sharply, and the current continues to increase unless the power supply is turned off. This effect is the locking effect. When the lock-in effect occurs, the internal current of the COMS can reach 40 mA or more, and it is easy to burn the chip.

Defensive measures:

1) Add a clamp circuit at the input and output terminals so that the input and output do not exceed the specified voltage.

2) Add a decoupling circuit to the power input terminal of the chip to prevent instantaneous high voltage on the VDD terminal.

3) Add a current-limiting resistor between VDD and the external power supply, and let it go in even if there is a large current.

4) When the system is powered by several power sources separately, the switch should be in the following order: when it is turned on, first turn on the COMS road power, then turn on the input signal and the load power; when it is off, first turn off the input signal and the load power, then Turn off the power to the COMS circuit.

6, the use of COMS circuit considerations

1) The voltage control device of the COMS circuit has a large input total resistance and a strong ability to capture interference signals. Therefore, do not use the unused pins. Connect a pull-up resistor or a pull-down resistor to give it a constant level.

2) When inputting a signal source with low internal resistance, connect a current limiting resistor between the input terminal and the signal source to limit the input current to 1mA.

3) When the long signal transmission line is connected, the matching resistor is connected at the COMS circuit.

4) When the input terminal is connected to a large capacitor, the resistor should be indirectly protected at the input and capacitor. The resistance value is R=V0/1mA. V0 is the voltage on the external capacitor.

5) If the input current of COMS exceeds 1 mA, it is possible to burn out COMS.

7, the input load characteristics of the TTL gate circuit (the processing of the input with a special case of resistance):

1) When floating, it is equivalent to the input terminal connected to the high level. Because this can be seen as an input that terminates an infinite resistor.

2) After inputting a 10K resistor in series with the input of the gate circuit, input a low level, and the input terminal presents a high level instead of a low level. Because the input load characteristic of the TTL gate circuit shows that the low-level signal input from the input terminal can be recognized by the gate circuit only when the series resistance of the input terminal is less than 910 ohms, and the input terminal is always presented when the series resistance is large. High level. This must be noted. The COMS gate circuit does not need to consider this.

8. The TTL circuit has an open collector OC gate. The MOS transistor also has an open-drain OD gate corresponding to the collector. Its output is called an open-drain output.

The OC gate has a leakage current output at the cutoff, which is the leakage current. Why is there a leakage current? That is because when the triode is turned off, its base current is about 0, but it is not really 0, after the triode. The current of the collector is not really 0, but about 0. And this is the leakage current.

Open-drain output: The output of the OC gate is the open-drain output; the output of the OD gate is also the open-drain output. It can absorb a lot of current, but it can't output current. Therefore, in order to input and output current, it should be used together with the power supply and the pull-up resistor. The OD gate is generally used as an output buffer/driver, level shifter, and to meet the need to sink large load currents.

9. What is the totem pole, and what is the difference between it and the open drain circuit?

In TTL integrated circuits, the output with the pull-up transistor is called the totem pole output, and the other is called the OC gate. Because TTL is a three-level switch, the totem pole is also connected by two three-stage push-pull. So push-pull is a totem. General totem output, high level 400UA, low level 8MA.

The unused input of the CMOS device must be connected to a high or low level. This is because CMOS is a high input impedance device. Ideally, there is no input current. If the unused input pin is left floating, it is easy to sense the interference signal. Affect the logic operation of the chip, even the static accumulation permanently breaks down this input, causing the chip to fail.

In addition, only the 4000 series CMOS devices can operate at 15 volts, the 74HC, 74HCT, etc. can only operate at 5 volts. Now there are CMOS logic chips that operate at 3 volts and 2.5 volts.

CMOS level and TTL level:

The CMOS logic level range is relatively large, ranging from 3 to 15V. For example, when the 4000 series is powered by 5V, the output is at a high level above 4.6, and the output is at a low level below 0.05V. The input is at a high level above 3.5V, and the input is at a low level below 1.5V.

For TTL chips, the power supply range is 0~5V, which is usually 5V. For example, 74 series 5V power supply, the output is high above 2.7V, the output is low below 0.5V, and the input is higher than 2V. Flat, low below 0.8V. Therefore, the CMOS circuit and the TTL circuit have a level shifting problem, so that the two level domain values ​​can be matched.

Some concepts about logic levels:

To understand the content of logic levels, you must first understand the meaning of the following concepts:

1. Input high level (Vih): The minimum input high level allowed when the logic gate input is high. When the input level is higher than Vih, the input level is considered high.

2. Input low level (Vil): The maximum input low level allowed when the logic gate input is low. When the input level is lower than Vil, the input level is considered low.

3. Output high level (Voh): The minimum value of the output level when the output of the logic gate is high. The level value of the logic gate output must be greater than this Voh.

4. Output low level (Vol): The maximum value of the output level when the output of the logic gate is low, and the level of the logic gate when the output of the logic gate is low must be less than this Vol.

5. Threshold level (Vt): There is a threshold level in the digital circuit chip, which is the level when the circuit has just barely flipped. It is a voltage value between Vil and Vih. For the threshold level of a CMOS circuit, it is basically one-half of the power supply voltage value, but to ensure a stable output, the input high level must be required > Vih , input low level

For general logic levels, the relationship of the above parameters is as follows:

Voh > Vih > Vt > Vil > Vol

6.Ioh: The load current (which is the pull current) when the logic gate output is high.

7. Iol: Load current when the logic gate output is low (sink current).

8.Iih: Current when the logic gate input is high (sink current).

9.Iil: Current when the logic gate input is low (current is drawn).

The gate output pole is directly connected to the output unit as an output terminal without a load resistor. This type of gate is called an open gate. The open TTL, CMOS, and ECL gates are called open collector (OC), open drain (OD), and open emitter (OE), respectively. When using, check whether pull-up resistors (OC, OD gates) or pull-down resistors are connected. (OE gate), and whether the resistance is appropriate. For open-collector (OC) gates, the pull-up resistor RL should meet the following conditions:

(1).RL < (VCC-Voh)/(n*Ioh+m*Iih)

(2).RL > (VCC-Vol)/(Iol+m*Iil)

Where n: the number of open gates with lines and m; the number of inputs driven.

10. Commonly used logic levels

Logic level: TTL, CMOS, LVTTL, ECL, PECL, GTL; RS232, RS422, LVDS, etc.

• The logic levels of TTL and CMOS can be divided into four categories according to typical voltage: 5V series (5V TTL and 5V CMOS), 3.3V series, 2.5V series and 1.8V series.

• 5V TTL and 5V CMOS logic levels are common logic levels.

• Logic levels of 3.3V and below are referred to as low voltage logic levels and are commonly used for LVTTL levels.

· Low voltage logic levels are also available in 2.5V and 1.8V.

• ECL/PECL and LVDS are differential inputs and outputs.

RS-422/485 and RS-232 are serial interface standards, RS-422/485 is differential input and output, and RS-232 is single-ended input and output.

OC gate, also known as open collector (open drain) NAND gate circuit, Open Collector (Open Drain).

Why introduce OC gates?

In actual use, it is sometimes necessary to connect two or more NAND gate outputs on the same wire, and the data on these NAND gates (state levels) are sent out by the same wire. Therefore, a new NAND gate circuit, the OC gate, is needed to implement "line and logic."

The OC gate is mainly used in three aspects:

1, the implementation of NAND or non-logic, used for level conversion, used as a driver. Since the collector of the output tube of the OC gate circuit is suspended, an external pull-up resistor Rp needs to be connected to the power supply VCC. The OC gate uses a pull-up resistor to output a high level. In addition, in order to increase the driving capability of the output pin, the selection principle of the pull-up resistor value should be large enough to reduce the power consumption and the current sinking capability of the chip; The drive current considerations should be small enough.

2, the line and logic, that is, the two outputs (including more than two) directly interconnected can achieve the "AND" logic function. In practical applications such as bus transmission, the output terminals of multiple gates need to be connected in parallel, and the general TTL gate outputs cannot be directly connected in parallel. Otherwise, the output tubes of these gates form a large short-circuit current due to low impedance. Current), which burns out the device. In hardware, it can be implemented with an OC gate or a three-state gate (ST gate). To achieve line and OC gates, a pull-up resistor should be added to the output port.

3. The three-state gate (ST gate) is mainly used in multiple gate output shared data buses. In order to avoid multiple gate outputs occupying the data bus at the same time, only one of the enable signals (EN) of these gates is allowed to be valid. Flat (such as high level), because the output of the tri-state gate is a push-pull low-impedance output, and does not need to be connected to the pull (load) resistor, the switching speed is faster than the OC gate, and the tri-state gate is often used as the output buffer.

What is OC, OD?

Open collector gate (collector open OC or open drain OD)

Open-Drain is the open-drain output, which is equivalent to the open-collector output, which is the open collector (OC) output in TTL. Generally used for line or line, and also for current drive.

Open-Drain is for MOS tubes, Open-Collector is for bipolar tubes, there is no difference in usage.

Open-drain circuits have the following characteristics:

a. Reduce the drive inside the IC by using the drive capability of the external circuit. Or drive a load higher than the chip supply voltage.

b. It is possible to connect Pins of multiple open-drain outputs to one line. Through a pull-up resistor, a "logical" relationship is formed without adding any devices. This is also the principle that I2C, SMBus and other buses determine the bus occupancy status. If the totem output is connected, a pull-up resistor must be connected. When the capacitive load is connected, the falling delay is the transistor inside the chip, which is an active driving, and the speed is fast; the rising delay is a passive external resistor, and the speed is slow. If the speed requirement is high, the power consumption will be large. Therefore, the choice of load resistor must balance power consumption and speed.

c. You can change the transmission level by changing the voltage of the pull-up power supply. For example, a pull-up resistor can be used to provide a TTL/CMOS level output.

d. Open-drain Pin is not connected to an external pull-up resistor and can only output a low level. In general, open drain is used to connect different levels of devices for matching levels.

The normal CMOS output stage is the upper and lower tubes. The removal of the tube above is OPEN-DRAIN. The main purpose of this output is two: level shifting and line sum.

Since the drain is open, the post-stage circuit must be connected to a pull-up resistor, and the supply voltage of the pull-up resistor can determine the output level. This way you can convert at any level.

The line and function are mainly used when there are multiple circuits to pull down the same signal. If the circuit does not want to pull low, it outputs a high level because the tube above OPEN-DRAIN is removed, and the high level is externally connected. The pull-up resistor is implemented. (And the normal CMOS output stage, if one output is high and the other is low, it is equal to the power supply short circuit.)

OPEN-DRAIN provides a flexible output, but it also has its weakness, which is the delay of the rising edge. Because the rising edge charges the load through an external pull-up passive resistor, when the resistance is selected, the hour delay is small, but the power consumption is large; otherwise, the delay is large and the power consumption is small. Therefore, if there is a requirement for the delay, it is recommended to use the falling edge output.