During communication, RF interference at around 840MHz affects the serial communication port configured as a UART. Some people speculate that this is because noise is present in the UARTRX signal connected to the AD6903GPIO_1 pin when its frequency (RF) interference source occurs. The average voltage of the signal is far from the expected value, and the magnitude of the voltage offset depends on the power and frequency of the RF source.
Some customers report that the RF interference center around 840MHz affects the serial communication port configured as a UART between a modem containing an AD6903 (LeMansLCR+) digital baseband processor and a host processor.
Figure 2 shows how the UARTRX signal on the GPIO_1 pin of the AD6903 is affected when the RF power amplifier is turned on. In Figure 2, the UARTRX entering the AD6903 is shown in pink, the UARTTX signal from the host processor is shown in purple, the power amplifier enable is shown in yellow, and the AD6903VEXT power supply is shown in green.
Figure 2: RF Interference on the UART Communication Port
When the power amplifier is turned on (yellow), the UART data transfer from the TX pin of the host processor to the RX pin (pink) of the AD6903 has failed because the RX signal rises to the middle between the high and low levels. It is inconsistent with the TX signal (purple). During the second pulse, when the power amplifier is turned on, the TX pin of the main processor and the RX pin of the AD6903 should remain high; however, there is noise on the TX pin, and the RX signal drops to its high and low voltage. Flat middle position. Also note that the noise on the VEXT supply voltage (green) increases and its value rises slightly when the power amplifier is turned on.
However, the problem must be independent of the power amplifier's enable signal and the power amplifier of the same modem, because the RF energy from other nearby phones or signal generators can also affect the UARTRX signal entering the AD6903. When using a signal generator scan to check for the vulnerability to radio frequency interference, the worst case is found at about 840 MHz, and at higher frequencies or lower.
A series resistor of this signal between the main processor and the AD6903 is used to reduce the logic high level from 3.3V to 2.8V. The rated resistance of this resistor is 10kΩ. It can be replaced with a smaller resistor, including a 0Ω resistor, because lowering the resistance reduces noise, but this does not solve the problem unless a short-circuit is used instead.
This problem is not unique to the AD6903. Chips from other manufacturers have similar phenomena. For example, the same problem occurs on pin 37 of the SN74AVCA16425GR. Please refer to Figure 3 for its functional block diagram.
Figure 3: Functional block diagram of the SN74AVCA16425GR.
Here 1DIR, 2DIR is high, OE is low, so the operation is from port A to port B, and pin 37 (1A7) will receive data from another chipset. This means it is an input type.
The signal on pin 37 of the SN74AVCA16425GR is tested in the presence of RF interference in the vicinity, ie, by telephone call near the test point (within 5 meters). Figure 4 shows that when the device is not powered (I/O status is unknown), its output is abnormal; and Figure 5 shows the abnormality of its output when the device is powered (input state).
Figure 4: Low level rise.
Principle of interference
This "RF interference pick-up" behavior of the UARTRX signal entering the AD6903 is centered on a particular RF frequency, and these signal traces are not completely masked. This phenomenon can be explained: the printed wiring of the motherboard picks up interference because there are parasitic inductance, parasitic resistance and parasitic capacitance on the wire, and the two ends of the wire are connected with high impedance; one side is a 10kΩ resistor, and the other side It is a CMOS input. The wires on the board are like an antenna with a 1/4 wavelength response.
Figure 5: High level reduction.
In the customer module, when calculating the GPIO1 wire, the module is calculated by 30mm, while the main board is about 15mm. So it's no surprise that this line is able to pick up RF noise and be sensitive to 840MHz. For details, please refer to FIG. 6.
Figure 6: RF interference calculation formula.
According to the above theory, it is recommended to add a capacitor to the signal channel to dampen the RF interference oscillation. The role of the capacitor is to change the tuning frequency of the antenna and reduce the antenna impedance to reduce the antenna gain. We then heard the report that the noise was reduced to an acceptable level by selecting the appropriate capacitor.
The DC offset of this signal can be generated by the diode of any CMOS input-output pin. They are often referred to as ESD (electrostatic discharge) protection diodes, but when configured as outputs, they are actually the depletion region of the transistors used to control the pins; those transistors are often used for dual purposes, ie when configured as inputs Also acts as an ESD protection device on the pin. So they are indispensable in all CMOS input/output circuit structures. These diodes are forward biased and the signal is clamped when the amplitude of the signal causes the diode drop (approximately 0.6V) to rise above VEXT, or vice versa. In order for the amplitude of the signal to increase with increasing RF energy within the antenna band, the average voltage of the signal will be close to half the VEXT voltage.
This explanation tells us that the peak-to-peak value of the signal is from VEXT+0.6V to -0.6V. But the amplitude measured by the oscilloscope is much smaller. To explain why the amplitude is reduced, we estimate that this is due to the attenuation caused by the oscilloscope probe and the contact resistance, or the sampling rate of the digital oscilloscope is not enough, for example, it is to capture the complete signal near 1 GHz (especially for a given display window) At about 10ms), the actual sample rate may be much slower than the required 2G sample/second. This theory is described in Figure 7.
Figure 7: Interpretation description for DC voltage offset observations.
The RF interference signal is picked up by the printed conductor and fed into the chip. The standard chip input/output attenuator acts as a rectifier and is diode-biased as part of all CMOS input-output pins (chip inputs/outputs). The signal swing is clamped when the forward voltage exceeds the diode drop (approximately 0.6V) above VEXT or vice versa. At the same time, the oscilloscope and / or probe can not measure the frequency of the GHz level, and its performance is equivalent to a low-pass filter. As a result, abnormal voltages appear on the "some" input/output pins (depending on the printed conductors connected to the input/output pins and the EMC design level).
It has also been reported that replacing 10kΩ series resistors with 0Ω resistors does not eliminate interference or DC level offsets, but can be achieved with short wiring replacement. Note that those resistors can be interpreted, even for 0Ω resistors, which can cause parasitic inductance due to the package being connected in series with a certain amount of resistor. When considering high frequencies, this series RL component acts more like a low pass filter than a pure resistor. Therefore, it seems that the resistance component is still likely to have a considerable impedance in the RF band where interference occurs.
solution
There are two ways to reduce/eliminate these effects:
1. Eliminate/reduce "interference sources" and increase system immunity (EMC protection) capabilities, such as isolating RF circuits from other digital circuits, adding separate RF and baseband shielding areas, maintaining good grounding, and using EMC materials in cell phone enclosures .
2. In order to remove this "interference", a small capacitor should be used (note the capacitor is placed close to the I/O pin). Add a 27pf capacitor to ground near the (AD6903.GPIO1) (UART_Rx) test point. It can be seen from the oscilloscope measurements that the input/output DC offset is eliminated. And the corresponding bit error rate of the UART communication port is normal. Refer specifically to Figures 8 and 9.
Figure 8: Low level normal trace.
Figure 9: High level normal trace.
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