2.1 Basic block diagram
On the basis of the existing card on the transmitting LED display, where the design of a body without external memory card transmission LED display, as shown in FIG 1
Figure 1 LED display card schematic
The transmission card is composed of a DVI module, an FPGA controller, and two Gigabit network output modules. The DVl decoder chip transmits the decoded data and control signals to the FPGA controller. The FPGA caches through the internal RAM, and performs the operation of replacing the clock domain and the bit width conversion, and then outputs the processed data through the Gigabit network. For a real-time video source with a resolution of 1280×1024 and a refresh rate of 60 Hz, the vertical partition method is adopted here, that is, the full screen data is equally divided into two Gigabit network outputs, and each channel transmits 640×1024, as shown in FIG. 2 .
Figure 2 video data partition map
2.2 Implementation method
As seen from the basic block diagram of Figure 1, the design of the transmission card is not only the hardware platform, but also the design of the internal program of the FPGA controller. The internal block diagram of the FPGA controller of the sending card is shown in Figure 3.
Figure 3 Internal block diagram of the FPGA controller
The internal logic of the FPGA controller includes a data input module, a dual-port RAM and its control module, a 24-bit to 8-bit module, and a Gigabit network output module. The data input module allocates the input DVI signals (including data, clock, enable, and field sync signals) to the back-end RAM and RAM control modules, and controls the synchronization of the entire system; the RAM control module controls the read and write operations of the RAM. In particular, the control of the four states of starting write, write stop, start read, and read stop: the data output from the RAM is converted to the Gigabit network output module after parallel and serial conversion, and the Gigabit network output module is in accordance with a certain network format. The received data is packaged and output. The data partition is sent as shown in Figure 2. This method can divide the full screen data into two Gigabit network outputs on average. The following is a vertical partitioning method to analyze its data flow direction, clock change and transmission time difference. For one-way Gigabit network data, a dual-port RAM design is used, the RAM depth is set to 640, the input and output word lengths are both set to 24 bits, and the read/write clock and enable are independent, as shown in Figure 4.
Automatic soap dispenser foam Intelligent Dispenser
Soap Dispenser Holder
Ningbo ATAP Electric Appliance Co.,Ltd , https://www.atap-airfryer.com